Electronic devices with good dynamic performance, that is, devices with a high frequency or a high switching speed, usually have extremely small dimensions and very thin junctions. The double polysilicon self-aligned technique (or DPSA), which can produce vertical npn bipolar transistors with transition frequencies greater than 50 GHz by virtue of regions with very small vertical doping profiles and by virtue of the use of lithographic processes which can produce sub-micrometric geometrical arrangements, is known. An application of this technique which is described in the Applicant's European patent application EP 0709896 also enables lateral pnp bipolar transistors to be produced with a single additional step; although these lateral pnp bipolar transistors do not have dynamic performance comparable with that of the vertical npn transistors, they are suitable or use to form, for example, biasing circuits, current mirrors, and load devices for gain stages in the same integrated circuit, in combination with vertical npn transistors.
An additional step is required which includes a photolithographic process for forming a mask which screens the base channels of the lateral pnp transistors during the ion implantation which is necessary to form the intrinsic base regions of the vertical npn transistors.
In view of the fact that any step of a method for manufacturing an integrated circuit involves manipulations and contaminations of various kinds which reduce the final output of the method, the object of the present invention is to propose a method of doping by implantation in which it is possible avoid the use of a mask as an implantation screen.